1. Field of the Invention
The present invention is related to nonvolatile storage and more particularly to integrated circuit chips including nonvolatile storage such as one or more cells or an array of nonvolatile random access memory (NVRAM) cells.
2. Background Description
Nonvolatile floating gate storage devices, such as may be used for memory cells in a nonvolatile random access memory (NVRAM), are well known in the industry. In a typical NVRAM cell, the cell's conductive state is determined by charge or lack thereof on the storage device's floating gate. The floating gate is an electrically isolated gate of a Field Effect Transistor (FET) stacked in a two device NAND-like structure with the gate of a select device. Charge is forced onto or removed from the floating gate through a thin insulator layer that, during a normal read, isolates the gate electrically from other adjoining conductive layers. For example, a negatively (or positively) charged floating gate may be representative of a binary one state, while an uncharged floating gate may be representative of a binary zero state or, vice versa.
Typically, the select device in the NAND-like structure is connected to a word line. In typical state of the art designs, adjacent cells are connected to a common bit line. Each of the word lines is uniquely addressable and physically distinct. Intersection of each word line with each bit line provides unique cell selection for reading and writing the selected cell. For reading, a read voltage (e.g., Vhi or ground) is applied to a control gate (or program gate) that is capacitively coupled to floating gates of the nonvolatile devices of devices being read. Typically, the bit lines are pre-charged high. Thus, when a word line is raised, bit lines discharge for those devices programmed for zeros and do not those programmed for ones. For writing, a write voltage applied to the program gate is capacitively coupled to floating gates of the nonvolatile devices and, when the gate, source and drain voltages are biased properly, the charge changes on the floating gate, i.e., to write selected cells. Similarly, cells are biased to remove the charge from the floating gates during each erase.
The typically high voltages needed to write and erase each cell normally require a very complicated fabrication process. So, to minimize cell write voltages and for adequate read performance, the floating gate is large. Consequently, large floating gates account for much of the cell area for a typical NVRAM cell. While, reduced cell size cannot come at the expense of unacceptably degraded performance, designers normally strive for minimum cell size to achieve maximum cell density for reduced storage costs.
Thus, there is a need for smaller, denser NVRAM cells.